A semiconductor device configuring a drive circuit such as solenoid load mounted on a vehicle-mounted electrical control unit (ECU) is required to have a current drive capability with a high breakdown voltage of 30 V or more and a high ampere order and to absorb current energy generated at an output terminal in order to prevent erroneous operation or destruction.
Thus, there is known, for example, a technique in which an active clamp circuit is provided between the gate and the drain of a power transistor at the output stage and a gate voltage of the power transistor is increased to turn on the transistor (active clamp operation) when a voltage over an absolute maximum rating is generated at an output terminal due to application of a large inductive current noise, thereby absorbing current noise generated at the output terminal in the ground (see PTL 1, for example). Further, with the technique disclosed in PTL 1, also when a reflux path for letting a current flow from a solenoid load toward the high side is shut down during an abnormality, the active clamp operation is performed to absorb load energy, thereby preventing the low-side power transistor from being damaged.
Current energy (thermal destruction energy) capable of being absorbed by the power transistor during the active clamp operation is determined under the condition of generation of thermal runaway due to self-heating of the transistor, and its value can be generally increased by increasing the size of the transistor. However, there is a problem that an increase in size of the transistor can cause an increase in chip cost.
On the other hand, the power transistor with a relatively large size is different in its radiation property at a uniform current density in the transistor, and thus a large difference in temperature is caused between in the center region and in the surrounding region. That is, the temperature is higher and the thermal runaway is easily caused in the center region with low radiation property while the temperature is lower due to the radiation effect in the surrounding region. Consequently, there is a problem that the thermal destruction energy of the transistor cannot be increased according to the increase in size.
There are disclosed techniques for making a distribution of temperatures uniform in a transistor for the above problem (see PTL 2, for example). One of them is a method for increasing intervals of active regions of a transistor arranged in parallel in the center region and decreasing them in the surrounding region, and the other of them is a method for further reducing input power in the center region than input power in the surrounding region. With either method, consumed power per unit area is decreased from the surrounding region toward the center region thereby to make the distribution of temperatures uniform in the transistor, consequently enhancing thermal destruction energy of the transistor.
Further, there is disclosed a technique for providing a non-active region in the center region in a power transistor and forming a heat radiation electrode on the non-active region (see PTL 3, for example). The center region with higher temperature is deactivated, thereby lowering the temperature in the transistor and enhancing uniformity of the temperatures. Further, heat is radiated to the outside of the semiconductor via the heat radiation electrode, thereby further lowering the temperature. Consequently, thermal destruction energy of the transistor can be similarly increased.
Further, there is disclosed a technique in which high-side transistors and low-side transistors are alternately arranged and the source electrode of a high-side transistor and the drain electrode of a low-side transistor are assumed as one common electrode in order to reduce parasitic inductance between the transistors (see PTL 4, for example). With the technique, heat generated in the low-side transistors can be radiated to the high-side transistor regions, thereby increasing thermal destruction energy of the low-side transistors without increasing the chip size of the output circuit configured of the high-side transistors and the low-side transistors.